The present invention relates to apparatus and methods for an improved CMOS circuit. More particularly, the present invention relates to a new type of CMOS circuits that advantageously precharges its output nodes and evaluates its logic inputs using precharge and evaluate pulses that are delayed from one another in a frequency dependent manner.
In a CMOS dynamic logic circuit, an output node is typically precharged using a precharge clock during the circuit's precharge cycle. After precharging, logic inputs into the logic circuit are then evaluated using an evaluation clock during the circuit's evaluation cycle. To perform the above mentioned precharge and evaluation tasks, CMOS dynamic logic circuits typically employ two separate fixed delay clocks to precharge and evaluate their circuit stages. The evaluation and precharge clocks in dynamic logic circuits are considered fixed delay clock signals because they are delayed from one another by a fixed delay period.
To avoid a crowbar condition, i.e. the existence of an undesirable discharge path between V.sub.dd and V.sub.ss through the logic circuitry that may result in erroneous logic evaluations and a resultant increase in power consumption, it is important that the dynamic logic circuit terminates its precharge cycle well in advance of the evaluation cycle. In other words, it is important to make sure that the evaluation and precharge clocks are properly timed relative to one another and that there is an adequate safety margin between the times when precharge terminates and evaluation begins.
Generally speaking, the use of two clocks that are separated from one another by a fixed delay time period for precharging and evaluating a dynamic logic circuit is satisfactory if the delay time period is correctly determined during the design phase. To determine the appropriate delay for a given design, a circuit designer typically has to roughly calculate the fixed delay values in view of other circuit parameters for a given operating clock speed. The logic circuit is then simulated a number of times using different delay values. The optimal fixed delay time value for a given operating speed is that which yields the correct evaluation result while minimizing the required safety margin between the circuit's precharge and evaluation cycles. Once the correct delay time periods are determined, fixed delay elements, e.g. inverters, latches, and the like, may be fabricated to generate the appropriate precharge and evaluation clocks for that operating frequency.
However, the use of multiple fixed delay clocks for controlling evaluation and precharge has many drawbacks. For one, the determination of the optimal fixed delay values and safety margin values between clocks in order to guarantee correct evaluations without exacting an undue performance penalty is oftentimes a time consuming process. Further, these fixed delay time periods, being implemented via physical circuit elements, cannot be easily changed to accommodate changes in the circuit's operating speed or to optimize performance under certain conditions without undue design effort.
When the dynamic logic circuit is required to operate at a different clock frequency than the operating frequency at which fixed delay time periods were originally calculated, e.g. due to improvements in fabrication technologies or changes in system requirements, the fixed delay values have to be determined all over again to ensure that precharge and evaluation clocks are still properly timed relative to one another and that adequate safety margins still exist between the circuit's precharge and evaluation cycles. If it turns out that these delay values must be changed to ensure proper performance, new delay time periods typically must be calculated, the circuit re-simulated, and new elements physically fabricated in the logic circuit to create the proper fixed delay clocks although the functionality of logic circuit itself remains unchanged. In other words, if fixed delays are used to generate the precharge and evaluation clocks, a mere change in the logic circuit's operating speed may require a circuit designer to once again calculate new optimal delay values and physically change parts of the logic circuit.
Further, it is difficult to implement a circuit that is capable of evaluating multiple data cycles per system clock cycle using fixed delay clocks. The difficulty comes about as a result of the aforementioned inflexibility inherent in the generation and utilization of fixed delay clocks as well as the tendency of fixed delay clocks to be subject to process variations when fixed delay elements are fabricated.
Consequently, what is needed is an improved CMOS dynamic logic circuit that precharges its output nodes and evaluates its logic inputs using precharge and evaluate clocks that are delayed from one another in a frequency dependent manner. The improved logic circuit preferably ensures that the precharge cycle be terminated prior to the initiation of the evaluation cycle regardless of the operating frequency
Instead of using fixed delay elements for generating their precharge and evaluation clock pulses, the improved logic circuit advantageously utilizes a plurality of clocks, which are themselves delayed from one another in a frequency dependent manner, in order to generate its precharge and evaluation clocks. Further, because the delay time periods and margins of the improved circuit are elastic with respect to the operating frequency, the precharge cycle is guaranteed to end prior to the initiation of the evaluation cycle regardless of the operating frequency, and the improved logic circuit advantageously needs a smaller safety margin between the precharge and the evaluation pulse. When the required margins are reduced, the improved circuit may be operated at a higher operating frequency, thereby improving performance. Further, the inventive apparatus and method facilitates a more efficient evaluation of multiple data cycles per clock cycle.